Rated at 30 MIPS at a frequency of 40 MHz, the Field Programmable System Level Integration Circuit (FPSLIC) combines an 8-bit microcontroller with over 50 kgates of FPGA or PLD programmable logic.

Version 5.1 of the ispLEVER programmable logic design suite adds features that include a FPGA preference flow, enhanced timing-closure and design-fit capabilities, and an IP-delivery ...