Semiconductor Engineering

Scaling AI Infrastructure With PCIe Switches And Retimers

Build configurable PCIe subsystems spanning local expansion, shared resource domains, and longer-reach topologies.
Design-Reuse

PLDA demonstrates successful PCIe 5.0 Link Training at 32 GT/s with its PCIe 5.0 controller and Broadcom PHY

SAN JOSE, Calif. October 22, 2020 -- PLDA, the industry leader in PCI Express® controller IP solutions has today unveiled their PCIe 5.0 demonstration. The demo showcases stable PCIe 5.0 Link Training ...
Electronic Design

How PCIe Tech Can Help Build Machine-Learning Accelerators

How to build an ML accelerator chip using PCI Express. What is the training process for a machine-learning model? The emergence of complex models that need multiple accelerators. Machine-learning (ML) ...
Electronic Design

Mastering PCIe 6.0 Receiver Compliance: Key Challenges and Best Practices

PCIe 6.0 is moving from specification into formal compliance, raising the bar for receiver validation. As testing advances, engineering teams need repeatable workflows that account for tighter PAM4 ...
Semiconductor Engineering

PCIe 7.0: Speed, Flexibility & Efficiency For The AI Era

As the industry came together for PCI-SIG DevCon last month, one thing took center stage, and that was PCI Express 7.0. While still in the final stages of development, the world is certainly ready for ...
Pocket-lint

What is PCIe 5.0, and how is it different from previous generations?

A Features Writer at Pocket-lint.com, Abhinav Lal has over a decade of experience in tech journalism. He was formerly the Managing Editor & Product Head at NDTV Gadgets 360 and News Editor at Digit.in ...